Embodiments of the present invention generally relate to circuit design, and more specifically to a method and system for static timing analysis in circuit design.
Static Timing Analysis (STA) is an important part of circuit design. The main purpose of a STA process is calculating various timing performance indexes of circuit design by analyzing path delay in order to detect paths violating timing requirements. Calculating path delay of respective paths in circuit design is fundamental to STA. A path typically includes one or more devices, e.g., a gate. Path delay may be determined based on device delay in the path. Device delay may be pre-determined and stored, for example, stored in a standard cell library that is accessible and available during the STA process.
It is known that device delay always varies with different input patterns/conditions. With XOR3, for example, a delay from its first input to the output is always related to input values at the second input and third input. Specifically, if the input patterns at the second input and third input are “11” (i.e., the two input values are both “1”), “10” or “01” (i.e., one of the two input values is “0,” while the other is “1”) and the input pattern is “00” (i.e., the two input values are both “0”), the delays from the first input to the output are always different. The same scenario may also exist in other circuit devices.
In a traditional STA method, path delay is obtained by summing maximum device delays of respective devices in the path. In other words, each individual device is supposed to reach the maximum device delay. The path delay derived in this way will be subsequently used to determine whether the path satisfies the timing needs. However, the path delay derived from the traditional STA method of maximum device delay is always “pessimistic.” In other words, the actual maximum delay of the path may be less than the calculated path delay. For example, in certain cases, some devices in the path may reach the maximum device delay simultaneously. The pessimistic path delay calculation affects the accuracy of STA and likely implies a time violation that may not occur in reality. To this end, unnecessary efforts may be required to optimize the circuit design, which may likely increase the running time and wafer size.